VHDL Statements
Assert Statement assert condition 
  [report string] 
  [severity severity_expr];
 
Process Statement [process_label] 
process [(signal_name {, signal_name})] 
  {declaration} 
begin 
  {statement} 
end
Wenn eine Sensitivity-Liste angegeben wird, darf im Prozeßrumpf kein wait aufgerufen werden (auch nicht indirekt). 
Komponenten und Signale können nicht deklariert werden - sonst alles. 
Erlaubte Statements sind: assert, case, if, loop, null, procedure calls, simple signal assignments, variable assignments, wait
Null Statement null; macht überhauptnix
If Statement if conditon then 
  {statement} 
{elsif condition then 
  {statement}} 
[else 
  {statement}] 
end if;
 
Case Statement case expression is 
  case_alternative 
  {case alternative} 
end case; 
case_alternative: when choice {|choice} => {statement}
Alle Alternativen müssen abgefragt werden. Als default kann als choice others verwendet werden.
Indefinite Loop [loop_label:] loop 
  {statement} 
end loop [loop_label];
Das ist eine Endlosschleife.
Exit Statement exit [loop_label] [when condition];  
For Loop [loop_label:] for name in range loop 
  {statement} 
end loop [loop_label];
 
Return Statement return [expression]; Kann nur in Funktion oder Prozedur vorkommen.
Variable Assignment target := expression;  
Wait Statement wait 
  [on signal_name {signal_name}] 
  [until condition] 
  [for time];
 
Procedure Call [label:] procedure_name [(association_element {,association_element })]; Das Label kann nur in der entity, architecture declaration, block oder generate anweisung stehen.
Simple Signal Assignment target <= [transport] waveform;  
Conditional Signal Assignment [label:] 
  target <= [guarded] [transport] {waveform when condition else} waveform;
Entspricht einem "if"
Selected Signal Assignment with expression select 
  target <= [guardet] [transport] {waveform when choice{| choice},} waveform when choice{| choice};
Entspricht "case".
Component Instantiation Statement instantiation_label: component_name 
  [generic map (association_element {,association_element})] 
  [port map (association_element {,association_element})];
 
Generate Statement generate_label: generation_scheme generate 
  {statement} 
end generate [generate_label]; 
generation_scheme: for name in range 
generation_scheme: if condition
 
© Chris Hübsch 02.07.1997